Interconnects are inevitable in a VLSI design. Especially, in SoCs. Signals need to be routed between blocks using interconnects. Now, there are parasicitcs in all metals when electricity passes through them. These parasitics cause the delays in the metals when they are used as interconnects. In fact, these parasitics are responsible for the propagation delay and switching delays in the MOSFETs. For an interconnect,
Where t is the interconnect thickness, L is the interconnect length, W is the interconnect width and Rs is called the sheet resistance. But, we need to take the fringe capacitance into account when the interconnect is close to the substrate. Higher metals don’t experience much of fringe capacitance. The actual capacitance is given by
Time constant
Apart from these parasitics, when we deal with high frequency signals (fast switching), an inductance parameter comes into play. The propagation delay is affected by the inductance parameter in addition to the resistance and capacitance. For example, when VDD is supplied to the source terminal of a pMOS, the actual voltage available at the terminal is VDD – V(t) where V(t) is the voltage drop generated by the inductance given by, V(t) = L (di/dt). Therefore, the actual VDD available to the pMOS source is vdd = VDD – V(t). This happens to every gate and transistor in the fast switching network.
Another parameter known as the characteristic impedance comes into play for high speed signals. These are transmission line parameters usually dealt with in board level design. But, the moment rise time and fall times go below a certain limit, these parameters come into the picture. Proper impedance matching has to be done to avoid signal reflections and degradation. Generally, when
signal tr < 160ps,
R < 5Z0
tr or tf < 2.5tflight
we need to consider characteristic impedance (transmission line effects).
One more effect of high speed signals is the skin effect where the signal tends to flow on the surface of the wire for very high frequencies. What happens is that the resistance if the line is also dependent on the skin depth because it essentially reduces the wire width. Naturally, when the wire dimension is reduced the resistance is increased and distortion is experienced on the signal at high frequencies.
We can notice that the time constant Ƭ depends on R and C (and also L of the line at times) and becomes proportional to square of L
Ƭ ά L2
To model the interconnect delay, we divide the whole line into m RC rungs of a ladder network (Distributed model.) such that \
Rm = Rline/m
Cm = Cline/m
= 
As m approaches infinity for a long interconnect
From calculations propagation delay
so,
because pMOS gives the logic ’1′ and nMOS gives the logic ’0′.
Using the rise time and fall time delays the total propagation delay from input to output can be found by the formula
These are all dependent on the L and W parameters of the line using which we can alter the delays.
. Higher ABEC number is class 1 and lower ABEC number is class 6, class 1 being the best.
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